1. Field of the Invention
The invention relates to a method for using a self-aligned metallic mask for formation of a metal-oxide-semiconductor device, and more particularly a method for forming a shallow source/drain, lightly doped drain metal-oxide-semiconductor device having a self-aligned low-resistivity silicide/polysilicon gate for greater device speed.
2. Related Art
In the manufacture of semiconductor products, it is always highly desirable to reduce the number of masking levels in order to increase yield. It is also desirable to use metallic masks where possible during process steps because a non-metallic mask is erodible and pattern definitions on a semiconductor wafer are less sharp than the patterns formed using a metallic mask. Further, it is desirable to fabricate metal-oxide-semiconductor devices having shallow source and drain regions because their transistor electrical characteristics are more easily controlled in fine-line geometry devices. Furthermore, it is desirable to manufacture such devices with lightly doped source and drain regions (although both regions are lightly doped, such devices are commonly referred to as "lightly doped drain", or "LDD" devices) to prevent "hot electron" effects by reducing the electric field path to slow down electrons.
The present invention provides a means for fabricating shallow source/drain LDD semiconductor devices using a self-aligned metallic mask. In the process of providing such a self-aligned metallic mask, a self-aligned silicide is formed on the gates of each transistor structure. The silicide provides a low resistivity path, resulting in greater device speed.